Sedona Strategies Career Center:

Senior Physical Design Engineer

Job Reference: SS-1031
Company: Confidential
Location: US - California - San Francisco Bay Area
Function: Engineering
Industry: Broadband Communications
Salary: Competitive Compensation
Reports To: Director of Engineering

Job Description

Candidate will have 7+ years in physical design of deep submicron chips and demonstrated ability with multiple tapeouts; knowledge of ASIC physical design process, design/characterization back ground in I/Os, SRAMs and standard cell library. Additionally, knowledge of nanometer design rules and technologies and good automation skills. The candidate must have worked in 130nm process (prefer 90nm experience) have had exposure to flip-chip and other packaging technologies and have knowledge of synthesis, STA and verilog coding. Good written and verbal communications skills are essential as is being a self-starter, passion in his/her work, and the abillity to work with cross functional teams. An MS in Electrical Engineering or higher degree required.

As Senior Physical Design Engineer, candidate will work on p&r/circuit activities. He/she will be responsible for physical design of 0.13um and 90nm chips; activites to include validation of various 3rd party IP (I/Os, standard cells, memories), floorplanning, power grid design, place & route, static/dynamic IR analysis, EM analysis, physical verification.

Comments:
Our Client develops silicon solutions that are focused on delivering fiber-fast broadband access over existing copper lines. Founded in 1999 and based in Fremont, California, they have raised over $100 million in financing to date from blue-chip venture capital firms.

Candidates may submit resume to jobs@sedonastrategies.com or simply click Apply below. Please include Job Reference number and title in email.

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